What Is SerDes? The High-Speed Data Technology Powering AI Chips and Data Centers

Hello, this is MasterMind.

The AI semiconductor race is usually framed around one question: How much computing power can a chip deliver?

But there is another question becoming just as important.

How quickly can data move between those chips?

A powerful GPU is only useful if it can receive data, exchange information with other processors, communicate with the network, and return results without spending too much time waiting.

That challenge is becoming increasingly important as AI infrastructure scales from individual accelerators to enormous clusters containing thousands of interconnected processors.

One of the fundamental technologies behind those high-speed connections is SerDes, short for Serializer/Deserializer.

SerDes may not attract the same attention as GPUs or high-bandwidth memory, but it sits underneath technologies ranging from high-speed networking and PCIe to custom AI accelerators and data-center connectivity.

For investors trying to understand where the next AI infrastructure bottleneck could emerge, SerDes is worth understanding.

SerDes serves as a high-speed data highway connecting AI chips, HBM, network switches, storage, and data centers, enabling massive amounts of AI data to move efficiently across modern computing infrastructure.

Key takeaway: SerDes converts parallel data into high-speed serial signals for transmission and then reconstructs that data at the receiving end. As AI systems require increasingly massive amounts of data movement, SerDes is becoming an essential building block of high-performance computing and data-center infrastructure.

 

What Is SerDes?

SerDes stands for Serializer/Deserializer.

At its core, the technology converts multiple parallel data signals into a high-speed serial stream, sends that stream across a physical connection, and converts it back into parallel data at the destination.

Why is that necessary?

Imagine trying to move traffic across a bridge.

One approach would be to build a separate lane for every stream of traffic. As traffic increases, however, the bridge becomes wider, more expensive, and more difficult to manage.

SerDes takes a different approach.

Instead of continually adding physical lanes, it organizes the traffic into fewer lanes operating at dramatically higher speeds.

In simplified form

Parallel Data
     ↓
 Serializer
     ↓
High-Speed Serial Signal
     ↓
Physical Channel
     ↓
Deserializer
     ↓
Parallel Data

One important distinction is that SerDes is not data compression.

It does not necessarily reduce the amount of information being transmitted.

Instead, it changes how that information travels so that large amounts of data can move efficiently through a limited number of physical connections.

SerDes converts multiple parallel data lanes into a high-speed serial signal for transmission and reconstructs the original parallel data at the receiving end.

How Does SerDes Work?

The basic concept sounds simple, but modern high-speed SerDes design is technically demanding.

As transmission speeds increase, engineers must deal with signal loss, interference, timing errors, power consumption, and other physical limitations.

The process can be divided into several stages.

1. Serialization

Inside a semiconductor, data may be processed in parallel.

The serializer takes multiple parallel data streams and converts them into a much faster serial stream.

This allows a system to transmit large amounts of information without requiring a separate physical connection for every individual data stream.

2. High-Speed Signal Transmission

The serialized signal then travels across a physical channel such as a printed circuit board trace, cable, or another high-speed electrical connection.

This is where physics becomes increasingly important.

The faster the signal travels, the more difficult it becomes to preserve signal quality.

3. Signal Recovery

The receiving side must determine exactly what information was transmitted even after the signal has experienced degradation.

Technologies such as equalization help compensate for distortion, while Clock and Data Recovery, or CDR, helps recover timing information from the incoming signal.

4. Deserialization

Finally, the deserializer converts the high-speed serial stream back into a form that the receiving chip can process internally.

The fundamental purpose of SerDes is therefore straightforward

Move more data through fewer physical connections while maintaining speed, reliability, and power efficiency.

The SerDes process serializes parallel data, transmits it through a high-speed channel, recovers the signal and clock, and deserializes it at the destination.

Why Is SerDes Important for AI?

The importance of SerDes is closely connected to a fundamental shift in computing.

AI performance is no longer determined solely by the capabilities of an individual processor.

Modern AI systems increasingly depend on enormous networks of processors working together.

Data constantly moves across connections such as

GPU ↔ GPU

GPU ↔ CPU

Accelerator ↔ Accelerator

GPU ↔ Network

Server ↔ Server

Switch ↔ Switch

Data Center ↔ Data Center

As AI models become larger and AI clusters become more complex, the amount of data traveling through these connections increases substantially.

This creates a potential data-movement bottleneck.

 

Computing Power Is Useless When Processors Are Waiting

Imagine a company employing thousands of highly productive analysts but giving them information through an extremely slow communications network.

Their theoretical productivity might be enormous.

Their actual productivity would be much lower because employees would spend too much time waiting for information.

AI infrastructure faces a similar challenge.

A GPU can perform extraordinary amounts of computation, but if data cannot reach it quickly enough—or if results cannot move efficiently to other processors—the utilization of expensive computing resources can suffer.

That is why AI infrastructure is increasingly becoming a battle not only over compute, but also over connectivity.

As AI computing power expands, GPUs, HBM, CPUs, servers, and network switches generate increasing data traffic, making high-speed interconnects critical for reducing data bottlenecks.

Why SerDes Matters for AI Chips

For decades, one of the semiconductor industry's primary methods of improving performance was putting more transistors onto increasingly advanced process nodes.

That strategy remains important.

But modern computing is also becoming more distributed.

Instead of relying entirely on one monolithic processor, high-performance systems increasingly connect CPUs, GPUs, AI accelerators, networking silicon, memory, and specialized processors into larger computing architectures.

That changes the economics of semiconductor performance.

If multiple high-performance components must behave like one system, the connections between them become strategically important.

The faster computing becomes, the more valuable efficient data movement becomes.

This is one reason the AI semiconductor investment cycle has expanded beyond processors themselves.

Capital spending increasingly touches memory, advanced packaging, networking, interconnects, optical communications, power infrastructure, and cooling.

SerDes sits within this broader connectivity layer.

 

SerDes, PCIe, and CXL: What Is the Relationship?

Investors researching SerDes will frequently encounter terms such as PCI Express (PCIe) and Compute Express Link (CXL).

They are related, but they are not the same thing.

PCIe and CXL define important aspects of how devices communicate, while SerDes technology provides part of the physical foundation required to transmit high-speed signals.

As interface standards move toward higher speeds, the engineering challenge becomes significantly harder.

Higher transmission rates can mean greater signal loss, tighter timing requirements, and increased sensitivity to noise.

This is also why technologies such as PAM4, or Pulse Amplitude Modulation with four levels, have become increasingly important.

Traditional binary signaling represents information using two signal states.

PAM4 uses four amplitude levels, allowing more information to be transmitted per symbol.

The tradeoff is that the signal becomes more difficult to distinguish reliably.

As a result, advanced signal-processing and SerDes design capabilities become increasingly important as interface speeds rise.

 

SerDes and Optical Transceivers: What Is the Difference?

SerDes should also be distinguished from an optical transceiver.

The two technologies can participate in the same data path, but they perform different functions.

SerDes handles high-speed serialization and deserialization of data associated with electrical interfaces.

An optical transceiver converts electrical signals into optical signals—and vice versa—so information can travel efficiently over fiber.

A simplified data path might look like this

AI Processor
     ↓
   SerDes
     ↓
High-Speed Electrical Signal
     ↓
Optical Interface
     ↓
Optical Signal
     ↓
Fiber
     ↓
Network Switch or Another Server

This relationship becomes especially relevant as AI clusters grow.

Moving data over relatively short electrical connections is one challenge.

Moving enormous amounts of information between racks, switches, and increasingly large computing clusters creates another.

As electrical connectivity reaches practical limitations involving distance, power, and signal integrity, optical networking can become increasingly important.

 

What Determines SerDes Performance?

Investors should not evaluate SerDes technology based on headline transmission speed alone.

Several factors matter.

Data Rate per Lane

A lane represents an individual high-speed data path.

Increasing the amount of information that can travel through each lane allows systems to achieve greater bandwidth without proportionally increasing the number of physical connections.

Power Efficiency

Power consumption is becoming one of the largest constraints facing AI data-center expansion.

This makes energy consumed per transmitted bit increasingly important.

A faster interface may provide little economic advantage if the additional bandwidth requires disproportionately more electricity.

Signal Integrity

High-speed electrical signals degrade as they travel.

Maintaining low error rates despite noise, interference, and signal loss requires sophisticated engineering.

At very high speeds, signal integrity can become one of the most difficult parts of semiconductor and system design.

Reach

A connection between components located close together has different engineering requirements from a connection spanning longer distances.

The ability to maintain reliable transmission across the required distance therefore matters alongside raw speed.

Process Validation and Production Readiness

SerDes combines digital and analog or mixed-signal engineering.

That makes performance dependent not only on theoretical design but also on how the technology behaves on a particular semiconductor manufacturing process.

For customers, proven silicon and production qualification can therefore matter as much as an impressive laboratory specification.

 

Why SerDes IP Matters

Another term investors may encounter is SerDes IP.

In semiconductor design, intellectual property blocks allow chip designers to incorporate proven functions rather than developing every component from scratch.

High-speed SerDes can be particularly challenging to design because it combines several disciplines, including

• Analog and mixed-signal engineering
• High-speed digital design
• Signal integrity
• Power optimization
• Process-specific engineering
• Interface-standard compliance

For companies developing custom silicon, using validated SerDes IP can potentially shorten development timelines and reduce execution risk.

This becomes particularly relevant as U.S. hyperscalers and semiconductor companies continue investing in custom accelerators and specialized data-center silicon.

However, investors should avoid a simplistic conclusion that growing SerDes demand automatically makes every SerDes IP provider valuable.

The important questions are whether the technology is qualified on leading manufacturing processes, whether customers are actually deploying it, and whether those deployments generate sustainable licensing, royalty, or product revenue.

 

How SerDes Could Influence the Semiconductor Value Chain

SerDes itself is not a macroeconomic variable like interest rates or inflation.

It does not directly determine the value of the dollar, Treasury yields, gold, or Bitcoin.

Its investment relevance comes from something different

SerDes helps investors understand how AI infrastructure spending can spread through the semiconductor and data-center value chain.

Industry	Why SerDes Matters	What Investors Should Watch
AI accelerators	More processors require more high-speed connectivity	I/O performance and power efficiency
Networking silicon	AI clusters generate enormous east-west traffic	Bandwidth growth and SerDes capability
Foundries	Advanced chips require validated interface IP	Process-specific IP ecosystems
Custom ASICs	Hyperscalers are developing specialized silicon	High-speed interface capabilities
PCIe / CXL ecosystem	Faster standards increase PHY complexity	Adoption of next-generation interfaces
Optical networking	Larger clusters require greater network bandwidth	800G, 1.6T and future architectures
Data centers	More compute creates networking and power requirements	Infrastructure capital spending
Automotive computing	Sensors and processors generate increasing data	High-speed, low-latency connectivity

The broader AI infrastructure cycle can be thought of as a chain

More AI Compute
      ↓
More GPUs and Accelerators
      ↓
More Memory Bandwidth
      ↓
More Data Movement
      ↓
Faster Interconnects
      ↓
More Network Bandwidth
      ↓
More Optical Connectivity
      ↓
More Power and Cooling Infrastructure

This chain reveals an important principle for technology investors.

Capital does not remain permanently concentrated in the most visible component of a technology cycle. It tends to spread toward whatever bottleneck is preventing the system from scaling further.

 

What Investors Should Watch

The long-term SerDes opportunity should be evaluated through several structural questions.

1. How Quickly Are Interface Standards Advancing?

Higher-speed generations of PCIe, Ethernet, CXL, and other interfaces raise the technical requirements for SerDes.

The harder those requirements become, the more valuable proven engineering capabilities can potentially become.

2. Can Companies Increase Speed Without Losing Power Efficiency?

AI data centers already face significant power constraints.

A SerDes architecture that increases bandwidth while maintaining strong energy efficiency may have an advantage over solutions focused purely on headline speed.

3. Is the Technology Actually Shipping?

The semiconductor industry frequently announces impressive specifications years before large-scale commercial deployment.

Investors should distinguish between

demonstration → qualification → customer adoption → volume production → meaningful revenue.

Those stages are not interchangeable.

4. Where Is the AI Bottleneck Moving?

This may be the most important question.

At one stage of the AI investment cycle, accelerator availability may be the primary constraint.

Later, memory bandwidth could become the bottleneck.

After that, networking, optical connectivity, power delivery, or cooling may become more important.

The bottleneck does not disappear.

It moves.

5. Does Industry Growth Translate Into Corporate Cash Flow?

A rapidly growing technology market does not guarantee strong shareholder returns for every company operating within it.

Investors still need to examine margins, competitive intensity, customer concentration, pricing power, R&D requirements, and free cash flow.

A great technology can still be a poor business if competition captures most of the economics.

AI infrastructure bottlenecks and capital spending can shift from GPUs and HBM toward SerDes, networking, optical interconnects, power, and cooling as computing systems continue to scale.

What Would Long-Term Capital Watch?

For long-term investors, the most useful way to think about SerDes is not as an isolated semiconductor technology.

It is part of a much larger question

Where does capital have to move next for AI infrastructure to continue scaling?

Follow the Flow of Capital

The first wave of AI infrastructure spending naturally concentrated around compute.

More compute created greater demand for high-bandwidth memory.

More GPUs and memory created more data traffic.

More traffic increased demand for high-speed networking.

Faster networks can drive additional demand for SerDes, switches, optical connectivity, and eventually power and cooling infrastructure.

One investment creates requirements for another.

Understanding this sequence can be more valuable than simply identifying which technology currently receives the most media attention.

 

Follow the Cash Flow

Technology leadership alone does not guarantee durable investment returns.

Investors should ask

• Is customer adoption producing real revenue?
• Does the company generate recurring licensing or royalty economics?
• Is free cash flow improving as the market expands?
• How concentrated is the customer base?
• Can the company remain competitive through the next interface generation?
• Does it possess pricing power, or is the technology becoming commoditized?

Look for Survivability

AI infrastructure may grow for many years while individual companies rise and disappear along the way.

Standards change.

Customers develop technology internally.

Competitors introduce alternatives.

Architectures evolve.

The investment question therefore goes beyond whether SerDes demand will increase.

A more useful question is

Which companies can remain strategically relevant as data rates, standards, manufacturing processes, and computing architectures continue changing?

 

The Bigger Investment Question

SerDes is ultimately an example of a broader principle that applies throughout technology investing.

When one bottleneck is solved, another tends to appear.

Compute can become constrained by memory.

Memory can become constrained by interconnect bandwidth.

Interconnects can become constrained by networking.

Networking can eventually run into optical, power, cooling, and physical infrastructure limitations.

That means investors should continually ask

If AI compute and data traffic continue increasing, what becomes scarce next?

And then ask a second question

Does the company I am studying merely benefit from the current AI narrative, or does it control an important part of the infrastructure that expanding AI systems must continue using?

That distinction matters.

Markets can reward narratives in the short run.

Over longer periods, sustainable value tends to depend much more heavily on competitive advantage, customer demand, and cash generation.

 

Conclusion

SerDes, or Serializer/Deserializer, converts parallel data into high-speed serial signals for transmission and reconstructs the data at the receiving end.

Its importance is increasing because modern AI systems are no longer simply collections of powerful processors.

They are enormous interconnected computing systems.

As GPU performance rises and AI clusters expand, moving data between processors, memory, servers, and networking equipment becomes increasingly difficult.

The AI infrastructure race is therefore evolving from a pure computing-power race into a broader competition involving compute, memory, connectivity, networking, optics, power, and cooling.

For investors, SerDes is valuable not because it provides an easy way to identify the next winning stock.

It is valuable because it helps explain how the architecture—and economics—of AI infrastructure are changing.

The key is to watch where bottlenecks emerge, where capital spending follows, and which companies can turn their technological position into durable cash flow.

In technology investing, predicting every winner is impossible.

Understanding where the next constraint may appear—and owning assets capable of surviving technological change—is far more important.

If there is one idea to remember, it is this

SerDes is one of the technologies that allows AI data to move at the speeds required by modern computing. As AI systems scale, the ability to move data efficiently may become just as strategically important as the ability to compute it.

This was MasterMind.